1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to a memory cell structure in a semiconductor memory device with a folded bit line structure suitable for high integration.
2. Description of the Prior Art
Conventionally, various memory cell structures have been proposed and put into practice for achieving high integration of a semiconductor memory device. For example, a memory cell structure is known in which adjacent memory cells are isolated by a groove region and the side walls of the groove region are utilized as a capacitor for storing information.
FIGS. 1A and 1B are diagrams showing a structure of a conventional highly integrated dynamic semiconductor memory device, where FIG. 1A is a top sectional view thereof, and FIG. 1B is a cross sectional view taken along a line X--X' in FIG. 1A. The conventional dynamic memory device as shown is disclosed in an article by F. Horiguchi et al., entitled "1 Mb DRAM with Folded Capacitor Cell Structure", ISSCC85 Digest of Technical Papers, Feb., 1985, pp. 244-245.
A memory cell comprises a capacitor portion C.sub.S for storing information in the form of charges and a transfer gate portion TR for transferring information to and from the capacitor portion C.sub.S. A groove isolation region 12 is formed around the memory cell. The groove region 12 is filled with a field oxide 2 serving as an insulator. Adjacent cells are electrically isolated by the field oxide 2.
The transfer gate portion TR comprises n.sup.+ -type diffusion regions 5a and 5b formed in a predetermined region of the p-type semiconductor substrate 1 and serving as a source and a drain, and a second polysilicon (polycristalline silicon) layer 7 formed on the p.sup.+ -type semiconductor substrate 1 between the diffusion regions 5a and 5b through a thin insulator film (gate dielectric film) and serving as a gate electrode.
The capacitor portion C.sub.S comprises a first polysilicon layer 3 serving as a cell plate of one electrode, the N.sup.+ -type diffusion region 5b serving as the other electrode, and a capacitor dielectric film 4 serving as a dielectric between these layers. The diffusion region 5b is also formed in the portion along the side walls of the groove 12. The first polysilicon layer 3 is formed so as to extend over and beyond the groove 12. Thus, the capacitor portion C.sub.S comprises capacitance C.sub.F formed of the diffusion region 5b and the first polysilicon layer 3 in a flat portion, and capacitance C.sub.P formed of the diffusion region 5b and the first polysilicon layer 3 on the side walls of the groove isolation region 12.
The N.sup.+ -type diffusion region 5a of the transfer gate TR is connected to a first aluminum interconnection layer 6 serving as a bit line through a contact hole 10. The gate electrode for turning the transfer gate TR on/off serves as a part of a word line 9. The word line 9 comprises the second polysilicon layer 7 and the second aluminum interconnection layer 8. The second polysilicon layer 7 and the second aluminum interconnection layer 8 are electrically connected at every constant distance, whereby the word line 9 is reduced in resistance.
In the foregoing, since the side walls of the groove isolation region 12 provided along the outer peripheral portion of the memory cell are utilized as capacitance C.sub.P, sufficiently wide operating margin and sufficient alpha particle immunity are ensured due to capacitance C.sub.P, even if the chip area and the cell size are reduced so that capacitance C.sub.S in the flat portion is reduced. The longer the peripheral length of the memory cell to be utilized is, the shallower the groove for obtaining the same quantity of capacitance C.sub.P can be.
A folded bit line structure has been proposed for high integration of a memory device.
FIGS. 2A and 2B are diagrams showing a structure of a memory cell which comprises a combination of a memory cell structure utilizing the side walls of the groove isolation region as capacitance and a folded bit line structure, where FIG. 2A is a plan view thereof and FIG. 2B is a cross sectional view taken along a line Y--Y' in FIG. 2A. Portions corresponding to those in FIGS. 1A and 1B have the same reference numerals in FIGS. 2A and 2B. In this structure, bit lines 6a and 6b comprising the first aluminum interconnection layer constitute a pair of complementary bit lines. The groove isolataion region 12 is formed on both sides of a channel region 11 of the transfer gate TR, whereby the channel region 11 is isolated from a capacitor portion of an adjacent memory cell. The first polysilicon layer 3 serving as a cell plate extends into the groove isolation region 12.
FIG. 3 is an enlarged cross sectional view in the neighborhood of the groove isolation region in FIG. 2A. As obvious from FIG. 3, the channel region 11 of the transfer gate TR is isolated from the capacitor portion o an adjacent memory cell by the groove isolation region 12. However, since a p-type diffusion layer serving as a channel stopper is not formed on the semiconductor substrate 1 in the groove isolation region 12, an inversion layer is liable to be formed in this portion. As a result, the leak current flows from an edge portion A of the channel region 11 through the inversion layer. In addition, the first polysilicon layer 3 serving as a cell plate must be terminated within the groove isolation region 12. Thus, if the groove isolation region 12 is formed with the minimum pattern width, it is difficult to perform an etching so as to terminate the first polysilicon layer 3 within the isolation region 12. Furthermore, since the channel region 11 is in contact with the groove region 12, the step in this portion is increased, so that it becomes difficult to pattern the second polysilicon layer 7 serving as a word line and being formed to extend over and beyond the channel region 11 and the groove isolation region 12. In order to avoid this, it is necessary to improve the process for filling the groove isolation region 12 with an insulator.